The present invention relates to a simulation method and a semiconductor device fabrication method, more specifically, a simulation method which can improve the simulation accuracy and a semiconductor device fabrication method using the simulation method.
As LSI is increasingly highly integrated, and the size of the semiconductor element formed in the LSI is more micronized, the accuracy of transferring patterns in the photolithography steps is becoming significant.
For example, a phenomenon that although the corners are set rectangular in the design step, the corners are rounded when transferred to a photoresist film on a wafer takes place. A phenomenon that the width of the micronized interconnections becomes larger or smaller than a design value takes place. These phenomena are called an optical proximity effect.
As the patterns are increasingly micronized, the optical proximity effect becomes serious, and often the sizes of patterns after etched fail to satisfy the allowable dimensions.
Then, a technique for decreasing the influence of the optical proximity effect, i.e., the OPC (Optical Proximity effect Correction) is noted. The OPC is a technique for correcting in advance a photomask to be used in the photolithography step so as to null such dimensional variation.
Recently, a technique for simulating patterns of an actually designed photomask on a wafer (photoresist film) when the photomask is transferred to the wafer is proposed.
If the simulation can be accurately made, the design efficiency can be improved.
Following references disclose the background art of the present invention.
[Patent Reference 1]
Specification of Japanese Patent Application unexamined Publication No. 2004-163472
However, the proposed simulation technique cannot always make the simulation with sufficiently high accuracy, and some error (fitting error) takes place between actually measured values of patterns given by transferring an actually designed photomask to a wafer (photoresist film) and computed values given by simulation.